A DCT Architecture based on Complex Residue Number Systems

In this paper a high-performance 1-D DCT processor is shown. It is based on a FFT algorithm that benefits from complex residue arithmetic to reduce the number of operations required. The array is based on the Quadratic Residue Number System (QRNS) which enables the implementation of complex adders (multipliers) with only two modular adders (multipliers). Thus, the number of additions and multiplications for the 8-point (16-point) processor was reduced in 21.43% (24.18%) and 24% (30.56%), respectively. An 8-point DCT array was developed for comparison using binary 2’s complement and the QRNS. The systems were modelled using VHDL and synthesized over Altera FLEX10KE Field-Programmable Logic (FPL) devices. The proposed array based on the QRNS yields a performance advantage of up to 81.84% over the equivalent system based on 2’s complement arithmetic. Key-Words: Residue Number System, DCT, QRNS, DSP, Field Programmable Logic.